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W78E858 Data Sheet 8-BIT MICROCONTROLLER
Table of Contents1. 2. 3. 4. 5. 6. GENERAL DESCRIPTION ......................................................................................................... 3 FEATURES ................................................................................................................................. 3 PIN CONFIGURATIONS ............................................................................................................ 4 PIN DESCRIPTION..................................................................................................................... 5 BLOCK DIAGRAM ...................................................................................................................... 6 FUNCTIONAL DESCRIPTION ................................................................................................... 6 6.1 6.2 RAM ................................................................................................................................ 6 EEPROM ........................................................................................................................ 7
6.2.1 6.2.2 6.2.3 6.2.4 Byte Write Mode ...............................................................................................................7 Page Write Mode..............................................................................................................7 Software Protected Data Write .........................................................................................7 Command Codes for Software Data Protection Enable/Disable and Software Erase.......7
6.3 6.4 6.5 6.6 6.7 6.8 6.9
Demo Code:.................................................................................................................... 8 On-chip Flash EPROM ................................................................................................. 11 Timers 0, 1, and 2......................................................................................................... 11 Clock ............................................................................................................................. 11 Crystal Oscillator........................................................................................................... 11 External Clock............................................................................................................... 11 Power Management...................................................................................................... 11
6.9.1 6.9.2 6.9.3 Idle Mode........................................................................................................................11 Power-down Mode..........................................................................................................12 Wake-up Via External Interrupts INT0 to INT9 ...............................................................12
6.10 6.11
Reset............................................................................................................................. 13 Pulse Width Modulator System .................................................................................... 14
6.11.1 6.11.2 PWMCON (91H)...........................................................................................................14 PWMP (92H) ................................................................................................................14 SFRAL (C4H) ...............................................................................................................16 SFRAH (C5H)...............................................................................................................16 SFRFD (C6H)...............................................................................................................16 SFRCN (C7H) ..............................................................................................................16 CHPCON (BFH) ...........................................................................................................17
6.12
In-system Programming System .................................................................................. 15
6.12.1 6.12.2 6.12.3 6.12.4
6.13 6.14 6.15 6.16
In-system Programming Mode Operating Table .......................................................... 16
6.13.1
MXPSR (A2H)............................................................................................................... 17 Interrupt System ........................................................................................................... 17 External Interrupts INT2 to INT9................................................................................... 18 Publication Release Date: May 5, 2004 Revision A4
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W78E858
6.16.1 6.16.2 6.16.3 6.16.4 6.16.5 IE_1 (E8H)....................................................................................................................18 IP1 (F8H)......................................................................................................................18 IX1 (E9H)......................................................................................................................19 IRQ1 (C0H) ..................................................................................................................19 Interrupt Priority and Vector Address............................................................................19 F04KBOOT Mode.........................................................................................................20 Lock Bit (Bit0) ...............................................................................................................21 MOVC Lock (Bit1) ........................................................................................................21 Scramble Enable (Bit2).................................................................................................21 Oscillator Gain Select (Bit7) .........................................................................................21 WDTC (8FH) ................................................................................................................22
6.17 6.18
F04KBOOT Mode (Boot From 4K Bytes LDROM) ....................................................... 20
6.17.1 6.18.1 6.18.2 6.18.3 6.18.4
Security ......................................................................................................................... 20
6.19 6.20 6.21 7. 7.1 7.2 7.3
Watch Dog Timer.......................................................................................................... 21
6.19.1
Programmable Clock-out .............................................................................................. 22 Reduce EMI Emission .................................................................................................. 22 Absolute Maximum Ratings .......................................................................................... 23 D.C. Characteristics...................................................................................................... 23 A.C. Characteristics ...................................................................................................... 25
7.3.1 7.3.2 7.3.3 7.3.4 7.3.5 7.3.6 Clock Input Waveform ....................................................................................................25 Program Fetch Cycle......................................................................................................25 Data Read Cycle ............................................................................................................26 Data Write Cycle.............................................................................................................26 Port Access Cycle ..........................................................................................................26 Flash Mode Timing .........................................................................................................26
ELECTRICAL CHARACTERISTICS......................................................................................... 23
8.
TIMING WAVEFORMS ............................................................................................................. 27 8.1 8.2 8.3 8.4 Program Fetch Cycle .................................................................................................... 27 Data Read Cycle........................................................................................................... 27 Data Write Cycle........................................................................................................... 28 Port Access Cycle......................................................................................................... 28 Expanded External Program Memory and Crystal ....................................................... 29 Expanded External Data Memory and Oscillator ......................................................... 30 40-pin DIP ..................................................................................................................... 31 44-pin PLCC ................................................................................................................. 31 44-pin PQFP ................................................................................................................. 32
9.
TYPICAL APPLICATION CIRCUITS ........................................................................................ 29 9.1 9.2
10.
PACKAGE DIMENSIONS ......................................................................................................... 31 10.1 10.2 10.3
11.
VERSION HISTORY ................................................................................................................. 33 -2-
W78E858
1. GENERAL DESCRIPTION
The W78E858 is an 8-bit microcontroller which has an in-system programmable Flash EPROM for firmware updating. The instruction set of the W78E858 is fully compatible with the standard 8052. The W78E858 contains a 32K bytes of main Flash EPROM and a 4K bytes of auxiliary Flash EPROM which allows the contents of the 32KB main Flash EPROM to be updated by the loader program located at the 4KB auxiliary Flash EPROM ROM; 768 bytes of on-chip RAM; 128 bytes of EEPROM, 8 extra power down wake-up through INT2 to INT9; 4 channel 8-bit PWM; four 8-bit bi-directional and bit-addressable I/O ports; an additional 4-bit port P4; three 16-bit timer/counters where the TIMER2 with programmable clock output and 17-bit watchdog timer are built in this device; a serial port. These peripherals are supported by a eight sources two-level interrupt capability. To facilitate programming and verification, the Flash EPROM inside the W78E858 allows the program memory to be programmed and read electronically. Once the code is confirmed, the user can protect the code for security.
2. FEATURES
* * * * * * * * * * * * * * * * * * * * Fully static design 8-bit CMOS micro-controller up to 40 MHz 32K bytes of in-system programmable FLASH EPROM for Application Program (APROM) 4K bytes of auxiliary FLASH EPROM for Loader Program (LDROM) Low standby current at full supply voltage 256 + 512 bytes of on-chip RAM 128 bytes on-chip EEPROM memory 64K bytes program memory address space and 64K bytes data memory address space Four 8-bit bi-directional ports One 4-bit bi-directional port Extra interrupts INT2 to INT9 at PORT1 Wake-up via external interrupts INT0 - INT9 Three 16-bit timer/counters One full duplex serial port Fourteen-sources, two-level interrupt capability Programmable Timer2 clock output via P1.0 17-bits watchdog timer Four channels 8-bit PWM Built-in power management Code protection Packaged in PDIP 40 / PLCC 44 / PQFP 44
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Publication Release Date: May 5, 2004 Revision A4
W78E858
3. PIN CONFIGURATIONS
P 1 . 4 6
P 1 . 3 5
P 1 . 2 4
T 2 E X . P 1 . 1 3
T 2 . P 1 . 0 2
PV 4D .D 2
A D 0 . P 0 . 0
A D 1 . P 0 . 1
A D 2 . P 0 . 2
A D 3 . P 0 . 3
P1.5 P1.6 P1.7 RST RXD, P3.0 P4.3 TXD, P3.1 IN T0, P3.2 IN T1, P3.3 T0, P3.4 T1, P3.5
7 8 9
1 44 43 42 41 40 39 38 37 36 35 34 33 32 31
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
10 11 12 13 14 15
44-pin PLCC
16 30 17 29 18 19 20 21 22 23 24 25 26 27 28 P 3 . 6 , / W R P 3 . 7 , / R D X T A L 2 X T A L 1 VP S4 S. 0 P 2 . 0 , A 8 P 2 . 1 , A 9 P 2 . 2 , A 1 0 P 2 . 3 , A 1 1 P 2 . 4 , A 1 2
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RST RXD , P3.0 TXD , P3.1 INT0, P3.2 INT1, P3.3 T0, P3.4 T1, P3.5 W R , P3.6 R D, P3.7 XTAL2 XTAL1 VSS
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 24 23 22 21
VC C P0.0, AD0 P0.1, AD1 P0.2, AD2 P0.3, AD3 P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13 P2.4, A12 P2.3, A11 P2.2, A10 P2.1, A9 P2.0, A8 P 3 . 6 , / W R P1.5 P1.6 P1.7 RST RXD, P3.0 P4.3 TXD, P3.1 IN T0, P3.2 IN T1, P3.3 T0, P3.4 T1, P3.5 1 2 3 4 5 6 7 8 9 10 11
P 1 . 4
T 2 E X . PP P 111 ... 321
T 2 . P 1 . 0
P 4 . 2
V D D
A D 0 . P 0 . 0
A D 1 . P 0 . 1
A D 2 . P 0 . 2
A D 3 . P 0 . 3
44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29
P0.4, AD4 P0.5, AD5 P0.6, AD6 P0.7, AD7 EA P4.1 ALE PSEN P2.7, A15 P2.6, A14 P2.5, A13
40-pin DIP
44-pin PQFP
28 27 26 25 24 23
12 13 14 15 16 17 18 19 20 21 22
P 3 . 7 , / R D
X T A L 2
X T A L 1
VP S4 S. 0
P 2 . 0 , A 8
P 2 . 1 , A 9
P 2 . 2 , A 1 0
P 2 . 3 , A 1 1
P 2 . 4 , A 1 2
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W78E858
4. PIN DESCRIPTION
SYMBOL TYPE DESCRIPTIONS External Access Enable: EA low forces the processor to execute the external ROM. The ROM address and data will not be present on the bus if the EA pin is high and the program counter is within the 32 KB area. Otherwise they will be present on the bus. Program Strobe Enable: PSEN enables the external ROM data in the Port 0 address/data bus. When internal ROM access is performed, no PSEN strobe signal outputs originate from this pin. Address Latch Enable: ALE is used to enable the address latch that separates the address from the data on Port 0. ALE runs at 1/6th of the oscillator frequency. An ALE pulse is omitted during external data memory accesses. RESET: A high on this pin for two machine cycles while the oscillator is running resets the device. RST has a Schmitt trigger input stage to provide additional noise immunity with a slow rising input voltage. Crystal 1: This is the crystal oscillator input. This pin may be driven by an external clock Crystal 2: This is the crystal oscillator output. It is the inversion of XTAL1. Ground: Ground potential. Power Supply: Supply voltage for operation. Port 0: Function is the same as that of the standard 8052. Port 1: Function is the same as that of the standard 8052. Port1 also service the alternative function INT2 - INT9. P1.0 provide a timer2 programmable clock output. Four channel PWM clock output via P1.4 - P1.7 Port 2: Port 2 is a bi-directional I/O port with internal pull-ups and emits the high-order address byte during accesses external memory Port 3: Function is the same as that of the standard 8052 Port 4: Function is the same as Port1
EA
I
PSEN
O/H
ALE
O/H
RST XTAL1 XTAL2 VSS VDD P0.0 - P0.7 P1.0 - P1.7 P2.0 - P2.7 P3.0 - P3.7 P4.0 - P4.3
I/L I O I I I/O D I/O H I/O H I/O H I/O H
* Note: TYPE I: input, O: output, I/O: bi-directional, H: pull-high, L: pull-low, D: open drain
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Publication Release Date: May 5, 2004 Revision A4
W78E858
5. BLOCK DIAGRAM
RAM 256 Bytes SFR Auxiliary RAM 512 RAM Bytes
256
PORT0 PROGRAMMABLE CLOCK OUTPUT PW M
EEPROM 128 Bytes
8051 CPU Core
Power Down W ake Up
INT2~9 TIMER2
PORT1
Auxiliary MTP-ROM 4K Bytes Main MTP-ROM 32K Bytes
Data Bus
UART INT0 INT1 TIMER1 TIMER0
PORT2
Interrupts
PORT3
W atch-dog
PORT4
6. FUNCTIONAL DESCRIPTION
The W78E858 architecture consists of a core controller surrounded by various registers, four 8-bit general purpose I/O ports, one 4-bits general purpose I/O port, 256 bytes data RAM and 512 bytes auxiliary RAM, 128 bytes embedded EEPROM memory, three timer/counters, one serial port, 17-bit watch-dog timer, 8-bit four channels PWM, programmable timer2 clock output, extra external interrupts INT2 to INT9, power-down wake up via external interrupts INT0 - INT9. The CPU supports 111 different op-codes and references both a 64K program address space and a 64 K data storage space.
6.1 RAM
The internal data RAM in W78E858 is 768 bytes. It is divided into two banks: 256 bytes of data RAM and 512 bytes of auxiliary RAM. These RAM are addressed by different ways. * * RAM 00H - 7FH can be addressed directly and indirectly as the same as in 80C51. Address pointers are R0 and R1 of the selected register bank. RAM 80H - FFH can only be addressed indirectly as the same as in 80C51. Address pointers are R0, R1 of the selected registers bank. memory with the MOVX instruction. Address pointers are R0 and R1 of the selected register bank and DPTR register. By setting ENAUXRAM flag in CHPCON register bit4 to enable on-chip auxiliary RAM 512 bytes. When the auxiliary RAM is enabled, the data and address will not appear on P0 and P2, they will keep their previous status that before the MOVX instruction be executed. Write the page select 00H or 01H to MXPSR register if R0 and R1 are used as address pointer. When the address of external data memory locations higher than 01FFH or disable auxiliary RAM 512 bytes micro-controller will be performed with the MOVX instruction in the same way as in the 80C51. The auxiliary RAM 512 bytes default is disabled after chip reset. -6-
* Auxiliary RAM 0000H - 01FFH is addressed indirectly as the same way to access external data
W78E858
6.2 EEPROM
The 128 bytes EEPROM is defined in external data memory space that located in FF80H-FFFFH in standard 8-bit series. It is accessed the same as auxiliary RAM512 bytes, the ENEEPROM flag in CHPCON register bit5 is set. Write the page select 03H to MXPSR register, R0 and R1are used as address pointer. The EEPROM provided byte write, page write mode and software write protection is used to protect the data lose when power on or noise. They are described as below:
6.2.1
Byte Write Mode
Once a byte write has been started, it will automatically time itself to completion. A BUSY signal (MXPSR.7) will be used to detect the end of write operation.
6.2.2
Page Write Mode
The EEPROM is divided into 2 pages and each page contains 64 bytes. The page write allows one to 64 bytes of data to be written into the memory during a single internal programming cycle. Page write is initiated in the same manner as byte write mode. After the first byte is written, it can then be followed by one to 63 additional bytes. If a second byte is written within a byte-load cycle time (TBLC) of 150us, the EEPROM will stay at page load cycle. Additional bytes can then be loaded consecutively. The page load cycle will be terminated and the internal programming cycle will start if no additional byte is load within 300us from the last byte be loaded. The address bit6 specify the page address. All bytes that are loaded to the buffer must have the same page address. The data for page write may be loaded in any order, the sequential loading is not required.
6.2.3
Software Protected Data Write
The EEPROM provides a JEDED-approved optional software-protected data write. Once this scheme is enabled, any write operation requires a series of three-byte program commands (with specific data to a specific address) to be performed before the data load operation. The three-byte load command sequence begins the page load cycle, without which the write operation will not activated. This write scheme provides optimal protection against inadvertent write cycles, such as cycles triggered by noise during system power-up or power-down. Once enabled, the software data protection will remain enabled unless the disable commands are issued. To reset the device to unprotected mode, a sixbyte command sequence is required. The address mapping of the external memory is given as following, if ENAUXRAM or ENEEPROM flags in CHPCON is not set, the CPU will access external memory instead of the on-chip memory. The data, address and read/write strobe signal will appear on relative IO port just like standard 80C52.
6.2.4
Command Codes for Software Data Protection Enable/Disable and Software Erase
BYTE ENABLE WRITE PROTECT ADDRESS FFD5H FFAAH FFD5H DATA AAH 55H A0H DISABLE WRITE PROTECT ADDRESS FFD5H FFAAH FFD5H FFD5H FFAAH FFD5H DATA AAH 55H 80H AAH 55H 20H SOFTWARE ERASE ADDRESS FFD5H FFAAH FFD5H FFD5H FFAAH FFD5H DATA AAH 55H 80H AAH 55H 10H
SEQUENCE 0 Write 1 Write 2 Write 3 Write 4 Write 5 Write
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Publication Release Date: May 5, 2004 Revision A4
W78E858
0000H
Auiliary RAM 512 Bytes
01FFH 0200H
External M em ory
FF80H
EEPROM 128 Bytes
FFFFH
(a) Standard 51 Series
Fig. On-Chip External Mem ory Addressed Mapping
6.3 Demo Code:
EEPROM_BASE EQU org 0000h jmp start: org FF80H start 500h
mov chpenr,#87h mov chpenr,#59h orl chpcon,#00100000b mov chpenr,#00h call enable_protect mov dptr,#EEPROM_BASE mov r0,#40h byte/page. Write from FF80h to FFBFh. mov r1,#55h call write_eeprom_block call enable_protect mov dptr,#EEPROM_BASE+40h mov r0,#40h address. mov r1,#55h call write_eeprom_block mov mov mov call jc mov mov anl mov clr jmp dptr,#EEPROM_BASE r0,#80h r1,#55h read_eeprom_block $error chpenr,#87h chpenr,#59h chpcon,#11011111b chpenr,#00h c $end -8-
; enable eeprom
; only write up to 64 ; write 55 data. ; Call it before writing ; Write from FFC0h to FFFFh
; disable eeprom
W78E858
$error:
$end:
mov mov anl mov setb
chpenr,#87h chpenr,#59h chpcon,#11011111b chpenr,#00h c
; disable eeprom
sjmp $ ;----------------------------------------------------------------disable_protect: mov dptr,#EEPROM_BASE+55h mov a,#aah movx @dptr,a mov dptr,#EEPROM_BASE+2ah mov a,#55h movx @dptr,a mov dptr,#EEPROM_BASE+55h mov a,#80h movx @dptr,a mov dptr,#EEPROM_BASE+55h mov a,#aah movx @dptr,a mov dptr,#EEPROM_BASE+2ah mov a,#55h movx @dptr,a mov dptr,#EEPROM_BASE+55h mov a,#20h movx @dptr,a call busy_waiting ret ;----------------------------------------------------------------eeprom_erase: mov dptr,#EEPROM_BASE+55h mov a,#aah movx @dptr,a mov dptr,#EEPROM_BASE+2ah mov a,#55h movx @dptr,a mov dptr,#EEPROM_BASE+55h mov a,#80h movx @dptr,a mov dptr,#EEPROM_BASE+55h mov a,#aah movx @dptr,a mov dptr,#EEPROM_BASE+2ah ;a5~a0 mov a,#55h movx @dptr,a mov dptr,#EEPROM_BASE+55h mov a,#10h movx @dptr,a call busy_waiting ret ;----------------------------------------------------------------Publication Release Date: May 5, 2004 Revision A4
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W78E858
enable_protect:
mov dptr,#EEPROM_BASE+55h mov a,#aah movx @dptr,a mov dptr,#EEPROM_BASE+2ah mov a,#55h movx @dptr,a mov dptr,#EEPROM_BASE+55h mov a,#a0h movx @dptr,a ret ;----------------------------------------------------------------busy_waiting: $wait1: mov a,mxpsr jnb acc.7,$wait1 $wait0: mov a,mxpsr jb acc.7,$wait0 ret ;---------------------------------------------------------------write_eeprom_block: ;input r0:counter ;input r1:pattern form ;input dptr:eeprom base address $write_loop: mov a,r1 movx @dptr,a inc dpl djnz r0,$write_loop call busy_waiting ret ;---------------------------------------------------------------read_eeprom_block: ;input r0:counter ;input r1:pattern form ;input dptr:eeprom base address ;output setb c --> fail push b $read_loop: movx a,@dptr mov b,a mov a,r1 cjne a,b,$error inc dpl djnz r0,$read_loop clr c jmp $end $error: setb c $end: pop b ret .end - 10 -
W78E858
6.4 On-chip Flash EPROM
The W78E858 includes two banks of FLASH EPROM. One is 32K bytes of main FLASH EPROM for application program (APROM) and another 4K bytes of FLASH EPROM for loader program (LDROM) when operating the in-system programming feature. In normal operation, the micro-controller will execute the code from the 32K bytes of APROM. By setting program registers, user can force CPU to switch to the programming mode which will execute the code (loader program) from the 4K bytes of auxiliary LDROM, and this loader program is going to update the contents of the 32K bytes of APROM. After chip reset, the micro-controller executes the new application program in the APROM. This in-system programming feature makes the job easy and efficient in which the application needs to update firmware frequently. In some applications, the in-system programming feature make it possible that end-user is able to easily update the system firmware by themselves without opening the chassis.
6.5 Timers 0, 1, and 2
Timers 0, 1, and 2 each consist of two 8-bit data registers. These are called TL0 and TH0 for Timer 0, TL1 and TH1 for Timer 1, and TL2 and TH2 for Timer 2. The TCON and TMOD registers provide control functions for timers 0, 1. The T2CON register provides control functions for Timer 2. RCAP2H and RCAP2L are used as reload/capture registers for Timer 2. The operations of Timer 0 and Timer 1 are the same as in the W78C51. Timer 2 is a 16-bit timer/counter that is configured and controlled by the T2CON register. Like Timers 0 and 1, Timer 2 can operate as either an external event counter or as an internal timer, depending on the setting of bit C/T2 in T2CON. Timer 2 has three operating modes: capture, auto-reload, and baud rate generator. The clock speed at capture or auto-reload mode is the same as that of Timers 0 and 1.
6.6 Clock
The W78E858 is designed to use with either a crystal oscillator or an external clock. Internally, the clock is divided by two before it is used by default. This makes the W78E858 relatively insensitive to duty cycle variations in the clock.
6.7 Crystal Oscillator
The W78E858 incorporates a built-in crystal oscillator. To make the oscillator work, a crystal must be connected across pins XTAL1 and XTAL2. In addition, a load capacitor must be connected from each pin to ground, and a resistor must also be connected from XTAL1 to XTAL2 to provide a DC bias when the crystal frequency is above 24 MHz.
6.8 External Clock
An external clock should be connected to pin XTAL1. Pin XTAL2 should be left unconnected. The XTAL1 input is a CMOS-type input, as required by the crystal oscillator. As a result, the external clock signal should have an input one level of greater than 3.5 volts.
6.9 Power Management
6.9.1 Idle Mode The CPU will enter to idle by setting the IDL bit in the PCON register. In the idle mode, the internal clock to the processor is stopped. The peripherals and the interrupt logic continue to be clocked. The processor will exit idle mode when either an interrupt or a reset occurs.
Publication Release Date: May 5, 2004 Revision A4
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W78E858
6.9.2 Power-down Mode When the PD bit of the PCON register is set, the processor enters the power-down mode. In this mode all of the clocks, including the oscillator are stopped. There are two ways to exit power-down mode, one is by a chip reset and another is via external interrupts wake up if the related control flags are enabled. 6.9.3 Wake-up Via External Interrupts INT0 to INT9
If the external interrupts INT0 to INT9 are enabled, the W78E858 can be awakened from power down mode with the external interrupts if the EA flag in IE register and related interrupt enable is set before enter power down mode. To ensure that the oscillator is stable before the controller starts, the internal clock will remain inactive for some oscillator periods. This is controlled by a on-chip delay counter. The delay time is software selectable and the reset default value is 1536 periods. By setting the PS2 - PS0 bits in AUXR register the delay periods is given as below: PS2 0 0 0 0 1 1 1 1 PS1 0 0 1 1 0 0 1 1 PS0 0 1 0 1 0 1 0 1 DELAY PERIODS 192 384 768 1536 3072 6144 12288 24576 DELAY TIME (20 MHZ) 0.0096 mS 0.0192 mS 0.0384 mS 0.0768 mS 0.1536 mS 0.372 mS 0.6144 mS 1.2288 mS
Power-Down
RESET-Pin Internal Clock Interrupt IN0~INT9 Oscillator ... ....
delay counter x Tosc Fig. Power-Down W ake Up Operation
> 24 x Tosc
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W78E858
P1.7
X9
P1.6
X8
P1.5
X7
P1.4
X6
P1.3
X5
P1.2
X4
P1.1
X3
P1.0
OR8
X2
IX1
IEN1
IRQ 1
W ake Up
Fig. Port1 External Interrupt Configuration
6.10 Reset
The external RST signal is sampled at S5P2. To take effect, it must be held high for at least two machine cycles while the oscillator is running. An internal trigger circuit in the reset line is used to deglitch the reset line when the RA80xx is used with an external RC network. The reset logic also has a special glitch removal circuit that ignores glitches on the reset line. During reset, the ports are initialized to FFH, the stack pointer to 07H, PCON (with the exception of bit 4) to 00H, and all of the other SFR registers except SBUF to 00H. SBUF is not reset. W78E858 Special Function Registers and Reset Values
F8 F0 E8 E0 +IP1 0000000 +B 00000000 +IE_1 00000000 +ACC 00000000 CHPENR 00000000 IX1 00000000 FF F7 EF E7
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Publication Release Date: May 5, 2004 Revision A4
W78E858
W78E858 Special Function Registers and Reset Values, continued D8 D0 C8 C0 B8 B0 A8 A0 98 90 88 80 +P4 11111111 +PSW 00000000 +T2CON 00000000 +IRQ1 00000000 +IP 000000 +P3 00000000 +IE 01000000 +P2 11111111 +SCON 00000000 +P1 11111111 +TCON 00000000 +P0 11111111 DF D7 T2MOD Xxxxxx0x RCAP2L 00000000 RCAP2H 00000000 TL2 00000000 SFRAL 00000000 TH2 00000000 SFRAH 00000000 CF SFRFD 00000000 SFRCN 00000000 CHPCON 0xx00000 C7 BF B7 AF MXPSR 0xxxxx00 SBUF xxxxxxxx PWMCON PWMP xxxx0000 00000000 TMOD TL0 00000000 00000000 SP DPL 00000111 00000000 A7 9F DAC0 00000000 TL1 00000000 DPH 00000000 DAC1 00000000 TH0 00000000 DAC2 00000000 TH1 00000000 DAC3 00000000 AUXR xxxx0110 97 WDTC 000xx000 PCON 00110000 8F 87
Note: the SFRs marked with a plus sign(+) are both byte and bit-addressable.
6.11 Pulse Width Modulator System
The pulse width modulator system of W78E858 contains four PWM output channels with a common 8bit counter. These channels generate pulses of programmable length and interval. The prescaler and counter are common to four PWM channels.
6.11.1 PWMCON (91H)
BIT 7-4 3 2 1 0 NAME PWM3 PWM2 PWM1 PWM0 FUNCTION Reverse Enable P1.7 as PWM clock output. Enable P1.6 as PWM clock output. Enable P1.5 as PWM clock output. Enable P1.4 as PWM clock output.
6.11.2 PWMP (92H)
The prescaler is loaded with the complement of the PWMP register during counter overflow. The repetition frequency is defined by 8-bit prescaler which clocks the counter. The prescaler division factor = (PWMP + 1). Reading the PWMP gives the current reload value. The actual count of the prescaler can't be read. The PWM counter is enabled with any bit PWMENn (n = 0, 1, 2, 3) of the PWMCON register. Output - 14 -
W78E858
to the port pin is separately enabled by setting the PWMENn bits in the PWMCON register. The PWM function is reset by a chip reset. In idle mode, the PWM will function as configurated in PWMCON. In power-down state of the PWM will freeze when the internal clock stops. If the chip is awakened with an external interrupt, the PWM will continue to function its state when power-down was entered. The repetition frequency is given by:
Fpwm = Fosc [255 x (1+PWMP)]
An oscillator frequency of 24 MHz results in a repetition range of 367.65 Hz to 94.12 KHz. The high/low ratio of PWMn is DACn/(255-DACn) for DACn values except 255. A DACn value 255 results in a high PWMn output.
Fosc
PW MEN0 PW MEN1 PW MEN2 PW MEN3 OR ENDAC AND
INTERNAL BUS
PW MP SFR
8-BIT PRESCALER
8-BIT UP CO UNTER
DAC0
8-BIT DETECT
O UTPUT BUFFER O UTPUT BUFFER OUTPUT BUFFER O UTPUT BUFFER
P1.4
DAC1
8-BIT DETECT
P1.5
DAC2
8-BIT DETECT
P1.6
DAC3
8-BIT DETECT
P1.7
Fig. Four Channels 8-Bit PW M Function Block Diagram
6.12 In-system Programming System
The W78E858 provided in-system programming function for new firmware updated. After the related register and flags are set, user can start timer and force the CPU enter idle mode, then W78E858 will perform the in-system program mode function specify in SFRCN register, the destination data and address will come from the related SFR. The CHPCON is read only by default. Firmware designer must write 87H, 59H sequentially to this Publication Release Date: May 5, 2004 Revision A4
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W78E858
special register CHPENR to enable the CHPCON write attribute, and write other value to disable CHPCON write attribute. This register protects from writing to the CHPCON register carelessly.
6.12.1 SFRAL (C4H)
The programming low-order byte address of FLASH EPROM in-system programming mode
6.12.2 SFRAH (C5H)
The programming high-order byte address of FLASH EPROM in-system programming mode
6.12.3 SFRFD (C6H)
The programming data for on-chip FLASH EPROM in-system programming mode
6.12.4 SFRCN (C7H)
BIT 7 NAME Reserve. On-chip FLASH EPROM bank select for in-system programming. 6 WFWIN = 0: 32K bytes FLASH EPROM bank is selected as destination for reprogramming. = 1: 4K bytes FLASH EPROM bank is selected as destination for reprogramming. 5 4 3-0 OEN CEN CTRL[3:0] FLASH EPROM output enable. FLASH EPROM chip enable. The flash control signals FUNCTION
6.13 In-system Programming Mode Operating Table
MODE Erase 32K APROM Erase 4K LDROM Program 32K APROM Program 4K LDROM Read 32K APROM Read 4K LDROM CTRL<3:0> 0010 0010 0001 0001 0000 0000 WFWIN 0 1 0 1 0 1 OEN 1 1 1 1 0 0 CEN 0 0 0 0 0 0 SFRAL X X Address Address Address Address SFRAH X X Address Address Address Address SFRFD X X Data In Data In Data Out Data Out
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W78E858
6.13.1 CHPCON (BFH)
BIT 7 6 5 4 3-2 1 NAME SWRESET FUNCTION When this bit is set to 1, and both FBOOTSL and FPROGEN are set to 1. It will enforce microcontroller reset to initial condition just like power on reset. (F04KMODE) This action will re-boot the microcontroller and start to normal operation. To read this bit can determine that the F04KBOOT mode is running. Reserve. ENEEPROM Enable on-chip 128 bytes EEPROM. ENAUXRAM Enable on-chip 512 bytes auxiliary RAM. FBOOTSL The loader program location selection. = 0: loader program in 32K memory bank. = 1: loader program in 4K memory bank. In system programming enable flag. 0 FPROGEN = 1: enable. The CPU switches to the programming flash mode after entering the idle mode and waken up from interrupt. The CPU will execute the loader program while in on-chip programming mode. = 0: disable. The on-chip FLASH EPROM read-only. In-system programmability is inhibit.
6.14 MXPSR (A2H)
BIT 7 6-2 NAME BUSY EEPROM BUSY signal. 1: EEPROM is writing. Reserved. Address pointer by MOVX instruction 0: read or write lower 256 byte Auxiliary RAM by pointer of R0 or R1 register 1-0 ADDRPNT 1: read or write Higher 256 byte Auxiliary RAM by pointer of R0 or R1 register 2: 128 byte EEPROM by pointer of R0 or R1 register FUNCTION
6.15 Interrupt System
External events and the real-time-driven on-chip peripherals require service by the CPU asynchronous to do execution of any particular section of code. To tie the asynchronous actives of these functions to normal program execution, a multiple-source, two-priority-level, nested interrupt system is provided. The W78E858 acknowledges interrupt requests from fourteen sources as below: * INT0 and INT1 Publication Release Date: May 5, 2004 Revision A4
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W78E858
* * * Timer0 and Timer1 UART serial I/O INT2 to INT9 (at Port1)
6.16 External Interrupts INT2 to INT9
Port1 lines serve an alternative purpose at eight additional interrupts INT2 to INT9. When enabled, each of these lines may "wake-up" the device from power-down mode. Using the IX1 register, the each pin may be initialized to either active HIGH or LOW. IRQ1 is the interrupt request flag register. Each flag, if the interrupt is enabled will be set on an interrupt request but must be cleared by software, i.e. via the interrupt software or when the interrupt is disable. The Port1 interrupts are level sensitive. A Port1 interrupt will be recognized when a level (HIGH or LOW depending on Interrupt Polarity Register IX1) on P1.x is held active for at least one machine cycle. The interrupt request is not served until the next machine cycle.
6.16.1 IE_1 (E8H)
BIT 7 6 5 4 3 2 1 0 NAME EX9 EX8 EX7 EX6 EX5 EX4 EX3 EX2 Enable external interrupt 9 Enable external interrupt 8 Enable external interrupt 7 Enable external interrupt 6 Enable external interrupt 5 Enable external interrupt 4 Enable external interrupt 3 Enable external interrupt 2 FUNCTION
6.16.2 IP1 (F8H)
BIT 7 6 5 4 3 2 1 0 NAME PX9 PX8 PX7 PX6 PX5 PX4 PX3 PX2 FUNCTION External interrupt 9 priority level External interrupt 8 priority level External interrupt 7 priority level External interrupt 6 priority level External interrupt 5 priority level External interrupt 4 priority level External interrupt 3 priority level External interrupt 2 priority level
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W78E858
6.16.3 IX1 (E9H)
BIT 7 6 5 4 3 2 1 0 NAME IL9 IL8 IL7 IL6 IL5 IL4 IL3 IL2 FUNCTION External interrupt 9 polarity level External interrupt 8 polarity level External interrupt 7 polarity level External interrupt 6 polarity level External interrupt 5 polarity level External interrupt 4 polarity level External interrupt 3 polarity level External interrupt 2 polarity level
6.16.4 IRQ1 (C0H)
BIT 7 6 5 4 3 2 1 0 NAME IQ9 IQ8 IQ7 IQ6 IQ5 IQ4 IQ3 IQ2 FUNCTION External interrupt 9 request flag External interrupt 8 request flag External interrupt 7 request flag External interrupt 6 request flag External interrupt 5 request flag External interrupt 4 request flag External interrupt 3 request flag External interrupt 2 request flag
6.16.5 Interrupt Priority and Vector Address
PRIORITY INTERRUPT VECTOR SOURCE PRIORITY INTERRUPT VECTOR SOURCE
1 2 3 4 5 6 7
INT0 INT5 TF0 INT6 INT1 INT2 INT7
0003H 0053H 000BH 005BH 0013H 003BH 0063H
External 0 External 5 Timer 0 External 6 External 1 External 2 External 7
8 9 10 11 12 13 14
TF1 SINT TF2 INT3 INT8 INT4 INT9
001BH 0023H 002BH 0043H 006BH 004BH 0073H
Timer 1 UART Timer 2 External 3 External 8 External 4 External 9
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W78E858
6.17 F04KBOOT Mode (Boot From 4K Bytes LDROM)
The W78E858 boots from APROM program (32K bytes bank) by default after chip reset. On some occasions, user can force the W78E858 to boot from the LDROM program (4K bank) after chip reset. The setting for this special mode is as follow.
6.17.1 F04KBOOT Mode
RST H H P4.3 X L P2.7 L X P2.6 L X MODE FO4KBOOT FO4KBOOT
Note: In application system design, user must take care the P2, P3, ALE, EA and PSEN pin status at reset to avoid W78E858 entering the programming mode or F04KBOOT mode in normal operation.
Enter 4K Reboot M ode Tim ing
P2.6
X
P2.7
Ts=1us Th > 24 clocks
X
RESET
6.18 Security
During the on-chip FLASH EPROM programming mode, the FLASH EPROM can be programmed and verified repeatedly. Until the code inside the FLASH EPROM is confirmed OK, the code can be protected. The protection of FLASH EPROM and those operations on it are described below: The W78E858 has several special setting registers in FLASH EPROM block. Those bits of the security register can't be changed once they have been programmed from high to low. They can only be reset through erase-all operation. The security register is located at the FFFFH on the same bank with 4K LDROM i.e., P3.6 must set high at writer mode.
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W78E858
0000H On-Chip 4KB LDROM 0FFEH
Reversed
Security Register
FFFFH
6.18.1 Lock Bit (Bit0)
This bit is used to protect the customer's program code in the W78E858. It may be set after the programmer finishes the programming and verifies sequence. Once these bits are set to logic 0, both the FLASH EPROM data and all data in FLASH EPROM block can't be accessed again.
6.18.2 MOVC Lock (Bit1)
When this bit is program to "0", the MOVC instruction will be disable when the program counter more than 7FFFh or EA pin is forced low.
6.18.3 Scramble Enable (Bit2) This bit is used to protect the customer's program code in the W78E858. If this bit is set to logic 0, the dump ROM code are scrambled by a scramble circuit and the dump ROM code will become a random ROM code. 6.18.4 Oscillator Gain Select (Bit7) If this bit is set to logic 0 (for 24 MHz), the EMI effect will be reduce. If this bit is set to logic 1 (for 40 MHz), the W78E858 could to use 40 MHz crystal, but the EMI effect is major. So we provide the option bit which could be chose by customer.
6.19 Watch Dog Timer
For more system reliability, W78E858 provides a programmable watch-dog time-out reset function. From programming prescaler select, user can choose a variable prescaler from divided by 2 to divided by 256 to get a suitable time-out period. The time-out period is given by:
Ttim e-out
=
1 Fosc
x2
14
x PRESCALER x 1000 x 12 (mS)
(Note: Fosc unit = Hz)
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W78E858
6.19.1 WDTC (8FH)
BIT 7 6 5 4-3 2 1 0
PS2 PS1
NAME ENW CLRW WIDL PS2 PS1 PS0
PS0
FUNCTION Enable watch-dog timer if set. Clear watch-dog timer and prescaler if set. This flag will be cleared automatically. If this bit is set, watch-dog is enabled under idle mode. If cleared, watch-dog is disable under idle mode. Default is cleared. Reversed. Watch-dog prescaler timer select. Watch-dog prescaler timer select. Watch-dog prescaler timer select.
PRESCALER SELCET WATCH-DOG TIME-OUT PERIOD (FOSC = 20 MHz)
0 0 0 0 1 1 1 1
0 1 0 1 0 0 1 1
0 0 1 1 0 1 0 1
2 4 8 16 32 64 128 256
19.66 mS 39.32 mS 78.64 mS 157.28 mS 314.57 mS 629.14 mS 1.25 mS 2.52 mS
6.20 Programmable Clock-out
A 50% duty cycle clock can be programmed to come out on P1.0. To configure the timer/counter2 as a clock generator, bit C/T2 in T2CON register must be cleared and bit T2OE in T2MOD register must be set. Bit TR2 (T2CON.2) also must be set to start timer. The clock-out frequency depends on the oscillator frequency and reload value of Timer2 capture register (RCAP2H, RCAP2L) as shown in this equation:
oscillatotr frequency 4 x (65536 - ( RCAP 2 H , RCAP 2 L))
In the clock-out mode, timer2 roll-overs will not generate an interrupt. This is similar to when it is used as a baud-rate generator. It is possible to use Timer2 as a baud-rate generator and a clock and a clock generator simultaneously.
6.21 Reduce EMI Emission
The transition of ALE will cause noise, so it cab be turned off to reduce the EMI emission if it is useless. Turn off the ALE signal transition only need too set the ALEOFF flag in the AUXR register When ALE is turned off, it will be reactived when program access external ROM or RAM data or jump to execute external ROM code. After access completely or program returns to internal ROM code, ALE signal will turn off again.
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W78E858
W IDL IDLE
EXTERNAL RESET SYSTEM RESET
Fosc
1/12 ENW
PRESCALER
14-BIT TIMER
CLRW
Fig. 17-BIT W atch-Dog Timer Function Block Diagram
7. ELECTRICAL CHARACTERISTICS
7.1 Absolute Maximum Ratings
PARAMETER DC Power Supply Input Voltage Operating Temperature Storage Temperature SYMBOL VDD - VSS Vin Ta Tst MIN. -0.3 VSS -0.3 0 -55 MAX. +6.0 VDD +0.3 70 +150 UNIT V V C C
Note: Exposure to conditions beyond those listed under Absolute Maximum Ratings may adversely affect the life and reliability of the device.
7.2 D.C. Characteristics
(VDD - VSS = 5V 10%, TA = 25 C, Fosc = 20 MHz, unless otherwise specified.)
PARAMETER Operating Voltage Operating Current Idle Current Power Down Current Input Current P1, P2, P3, P4 Input Current RST Input Leakage Current P0, EA
SYM. VDD IDD IIDLE IPWDN IIN1 IIN2 ILK
SPECIFICATION MIN. MAX. UNIT 4.5 5.5 V -50 -10 -10 20 6 50 +10 +300 +10 mA mA A A A A
TEST CONDITIONS RST = 1, P0 = VDD No load VDD = 5.5V Idle mode VDD = 5.5V Power-down mode VDD = 5.5V VDD = 5.5V VIN = 0V or VDD VDD = 5.5V 0 < VIN < VDD VDD = 5.5V 0 < VIN < VDD
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W78E858
D.C. Characteristics, continued
PARAMETER Logic 1 to 0 Transition Current P1, P2, P3, P4 Input Low Voltage P0, P1, P2, P3, P4, EA Input Low Voltage RST Input Low Voltage XTAL1[*4] Input High Voltage P0, P1, P2, P3, P4, EA Input High Voltage RST Input High Voltage XTAL1[*4] Output Low Voltage P1, P2, P3, P4 Output Low Voltage P0, ALE, PSEN Sink Current P1, P3, P4 Sink Current
[*3]
SYM. ITL[*4] VIL1 VIL2 VIL3 VIH1 VIH2 VIH3 VOL1 VOL2 ISK1 I SK2 VOH1 VOH2 ISR1 ISR2
SPECIFICATION MIN. MAX. UNIT -500 0 0 0 2.4 3.5 3.5 4 10 2.4 2.4 -120 -8 0.8 0.8 0.8 VDD +0.2 VDD +0.2 VDD +0.2 0.45 0.45 12 20 -250 -20 A V V V V V V V V mA mA V V A mA
TEST CONDITIONS VDD = 5.5V VIN = 2.0V VDD = 4.5V VDD = 4.5V VDD = 4.5V VDD = 5.5V VDD = 5.5V VDD = 5.5V VDD = 4.5V IOL = +2 mA VDD = 4.5V IOL = +4 mA VDD = 4.5V VIN = 0.45V VDD = 4.5V VIN = 0.45V VDD = 4.5V IOH = -100 A VDD = 4.5V IOH = -400 A VDD = 4.5V VIN = 2.4V (latch) VDD = 4.5V VIN = 2.4V
P0, P2, ALE, PSEN Output High Voltage P1, P2, P3, P4 Output High Voltage P0, ALE, PSEN [*3] Source Current P1, P2, P3, P4 Source Current P0, P2, ALE, PSEN
Notes: *1. RST pin is a Schmitt trigger input.
*3. P0, ALE and PSEN are tested in the external access mode.
*4. XTAL1 is a CMOS input. *5. Pins of P1, P2, P3, P4 can source a transition current when they are being externally driven from 1 to 0. The transition current reaches its maximum value when VIN approximates to 2V.
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W78E858
7.3 A.C. Characteristics
The AC specifications are a function of the particular process used to manufacture the part, the ratings of the I/O buffers, the capacitive load, and the internal routing capacitance. Most of the specifications can be expressed in terms of multiple input clock periods (TCP), and actual parts will usually experience less than a 20 nS variation. The numbers below represent the performance expected from a 0.6 micron CMOS process when using 2 and 4 mA output buffers.
7.3.1
Clock Input Waveform
XTAL1
T CH F OP, TCP T CL
PARAMETER Operating Speed Clock Period Clock High Clock Low
SYMBOL FOP TCP TCH TCL
MIN. 0 25 10 10
TYP. -
MAX. 40 -
UNIT MHz nS nS nS
NOTES 1 2 3 3
Notes: 1. The clock may be stopped indefinitely in either state. 2. The TCP specification is used as a reference in other specifications. 3. There are no duty cycle requirements on the XTAL1 input.
7.3.2
Program Fetch Cycle
PARAMETER SYMBOL TAAS TAAH TAPL TPDA TPDH TPDZ TALW TPSW MIN. 1 TCP- 1 TCP- 1 TCP- 0 0 2 TCP- 3 TCP- TYP. 2 TCP 3 TCP MAX. 2 TCP 1 TCP 1 TCP UNIT nS nS nS nS nS nS nS nS 4 4 NOTES 4 1, 4 4 2 3
Address Valid to ALE Low Address Hold from ALE Low ALE Low to PSEN Low
PSEN Low to Data Valid
Data Hold after PSEN High Data Float after PSEN High ALE Pulse Width
PSEN Pulse Width
Notes: 1. P0.0 - P0.7, P2.0 - P2.7 remain stable throughout entire memory cycle. 2. Memory access time is 3 TCP. 3. Data have been latched internally prior to PSEN going high. 4. "" (due to buffer driving delay and wire loading) is 20 nS.
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Publication Release Date: May 5, 2004 Revision A4
W78E858
7.3.3 Data Read Cycle
PARAMETER ALE Low to RD Low
RD Low to Data Valid
SYMBOL Tdar Tdda Tddh Tddz Tdrd
MIN. 3 TCP- 0 0 6 TCP-
TYP. 6 TCP
MAX. 3 TCP+ 4 TCP 2 TCP 2 TCP -
UNIT nS nS nS nS nS
NOTES 1, 2 1
Data Hold from RD High Data Float from RD High
RD Pulse Width
2
Notes: 1. Data memory access time is 8 TCP. 2. "" (due to buffer driving delay and wire loading) is 20 nS.
7.3.4
Data Write Cycle
PARAMETER SYMBOL TDAW TDAD TDWD TDWR MIN. 3 TCP- 1 TCP- 1 TCP- 6 TCP- TYP. 6 TCP MAX. 3 TCP+ UNIT nS nS nS nS
ALE Low to WR Low Data Valid to WR Low Data Hold from WR High
WR Pulse Width
Note: "" (due to buffer driving delay and wire loading) is 20 nS.
7.3.5
Port Access Cycle
PARAMETER SYMBOL TPDS TPDH TPDA MIN. 1 TCP 0 1 TCP TYP. MAX. UNIT nS nS nS
Port Input Setup to ALE Low Port Input Hold from ALE Low Port Output to ALE
Note: Ports are read during S5P2, and output data becomes available at the end of S6P2. The timing data are referenced to ALE, since it provides a convenient reference.
7.3.6
Flash Mode Timing
PARAMETER SYMBOL TRV TEFRL TPPH TPPL TEPL TRPL TAPF TDR MIN. 9 9 18 40 25 1.35 45 81 TYP. 10 10 20 50 30 1.5 50 90 MAX. 11 11 22 60 50 1.65 55 99 UNIT S S S S mS S nS nS NOTES -
Reset Valid Enter Flash Mode Reset Low Program Pulse High Program Pulse Low Erase Pulse Low Read Pulse Low Address PreFix Data Remain
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W78E858
8. TIMING WAVEFORMS
8.1 Program Fetch Cycle
S1 XTAL1
S2
S3
S4
S5
S6
S1
S2
S3
S4
S5
S6
T ALW ALE T APL PSEN T PSW T AAS PORT 2 T AAH PORT 0 Code A0-A7 Data A0-A7 Code A0-A7 Data A0-A7 T PDA T PDH, T PDZ
8.2 Data Read Cycle
S4 XTAL1 ALE PSEN PORT 2
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15 A0-A7 DATA T DAR T DDA
PORT 0 T DDH, T DDZ RD T DRD
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W78E858
Timing Waveforms, continued
8.3 Data Write Cycle
S4 XTAL1 ALE PSEN PORT 2 PORT 0 WR
S5
S6
S1
S2
S3
S4
S5
S6
S1
S2
S3
A8-A15
A0-A7
DATA OUT
TDAD
T DW D
T DAW
T DW R
8.4 Port Access Cycle
S5 XTAL1
S6
S1
ALE T PDS PORT T PDH T PDA DATA OUT
INPUT SAMPLE
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W78E858
9. TYPICAL APPLICATION CIRCUITS
9.1 Expanded External Program Memory and Crystal
V DD V DD 35 21 10 u R 22
CRYSTAL
EA XTAL1 XTAL2 RST INT0 INT1 T0 T1 P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 W78E858
8.2 K C1 C2
10
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7 P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7 RD WR PSEN ALE TXD RXD
43 42 41 40 39 38 37 36 24 25 26 27 28 29 30 31 19 18 32 33 13 11
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7 A8 A9 A10 A11 A12 A13 A14 A15
AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 A0 5 A1 6 A2 9 A3 12 A4 15 A5 16 A6 19 A7
14 15 16 17 2 3 4 5 6 7 8 9
GND 1 OC 11 G 74LS373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 27 A15 1 GND 20 22
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14 A15 CE OE 2764
O0 O1 O2 O3 O4 O5 O6 O7
11 12 13 15 16 17 18 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
Figure A
CRYSTAL 6 MHz 16 MHz 24 MHz 32 MHz 40 MHz
C1 68P - 100P 20P - 100P 10P - 68P 5P - 20P 5P
C2 68P - 100P 20P - 100P 10P - 68P 5P - 20P 5P
R 6.8K 6.8K 6.8K 6.8K 3.3K
Above table shows the reference values for crystal applications.
Notes:
1. C1, C2, R components refer to Figure A 2. Crystal layout must get close to XTAL1 and XTAL2 pins on user's application board.
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W78E858
Typical Application Circuits, continued
9.2 Expanded External Data Memory and Oscillator
VDD VDD
35
EA
21
10 u OSCILLATOR
XTAL1
20
8.2 K
XTAL2
10 RST
P0.0 P0.1 P0.2 P0.3 P0.4 P0.5 P0.6 P0.7
43 42 41 40 39 38 37 36
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
14 15 16 17
INT0
INT1 T0 T1
2 3 4 5 6 7 8 9
P1.0 P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7
P2.0 P2.1 P2.2 P2.3 P2.4 P2.5 P2.6 P2.7
24 25 26 27 28 29 30 31
A8 A9 A10 A11 A12 A13 A14
AD0 3 AD1 4 AD2 7 AD3 8 AD4 13 AD5 14 AD6 17 AD7 18 GND 1
D0 D1 D2 D3 D4 D5 D6 D7
Q0 Q1 Q2 Q3 Q4 Q5 Q6 Q7
2 5 6 9 12 15 16 19
A0 A1 A2 A3 A4 A5 A6 A7
OC 11 G
74LS373
A0 10 A1 9 A2 8 A3 7 A4 6 A5 5 A6 4 A7 3 A8 25 A9 24 A10 21 A11 23 A12 2 A13 26 A14 1
A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 A13 A14
D0 11 D1 12 D2 13 D3 15 D4 16 D5 17 D6 18 D7 19
AD0 AD1 AD2 AD3 AD4 AD5 AD6 AD7
RD
WR PSEN ALE TXD RXD
19 18 32 33 13 11
GND 20 22 27
CE OE
WR 20256
W78E858
Figure B
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W78E858
10. PACKAGE DIMENSIONS
10.1 40-pin DIP
Symbol
Dimension in inch Dimension in mm Min. Nom. Max. Min. Nom. Max.
0.210 0.010 0.150 0.016 0.048 0.008 0.155 0.018 0.050 0.010
2.055 0.590 0.600
D 40 21
E1
A A1 A2 B B1 c D E E1 e1 L
a
5.334 0.254
0.160 0.022 0.054 0.014
2.070
3.81 0.406 1.219 0.203
3.937 0.457 1.27 0.254
52.20 15.24
4.064 0.559 1.372 0.356
52.58 15.494
0.610 14.986
0.540
0.090
0.545
0.100
0.550
0.110
13.72
2.286
13.84
2.54
13.97
2.794
0.120
0 0.630
0.130
0.140
15
3.048
0 16.00
3.302
3.556
15
1 S A A2 L B B1 e1
20 E c A1
eA S
Notes:
0.650
0.670
0.090
16.51
17.01 2.286
Base Plane
Seating Plane
a
eA
1. Dimension D Max. & S include mold flash or tie bar burrs. 2. Dimension E1 does not include interlead flash. 3. Dimension D & E1 include mold mismatch and . are determined at the mold parting line. 4. Dimension B1 does not include dambar protrusion/intrusion. 5. Controlling dimension: Inches. 6. General appearance spec. should be based on final visual inspection spec.
10.2 44-pin PLCC
HD D
6 1 44 40
Symbol
7 39
Dimension in inch Min. Nom. Max.
0.185 0.020 0.145 0.026 0.016 0.008 0.648 0.150 0.028 0.018 0.010 0.653 0.155 0.032 0.022 0.014 0.658
Dimension in mm Min. Nom. Max.
4.699 0.508 3.683 0.66 0.406 0.203 16.46 3.81 0.711 0.457 0.254 16.59 3.937 0.813 0.559 0.356 16.71
E
HE
GE
17
29
18
28
c
A A1 A2 b1 b c D E e GD GE HD HE L y
Notes:
0.648
0.590
0.653
0.658
16.46
14.99
16.59
16.71
16.00
0.050
BSC 0.630
1.27
BSC
0.610
15.49
0.590
0.680
0.610
0.690
0.630
0.700
14.99
17.27
15.49
17.53
16.00
17.78
0.680
0.090
0.690
0.100
0.700
0.110 0.004
17.27
2.296
17.53
2.54
17.78
2.794 0.10
L A2 A
e
Seating Plane GD
b b1
A1 y
1. Dimension D & E do not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection spec.
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W78E858
Package Dimensions, continued
10.3 44-pin PQFP
HD D
44 34
Dimension in inch
Dimension in mm
Symbol
Min. Nom. Max.
--0.002 0.075 0.01 0.004 0.390 0.390 0.025 0.510 0.510 0.025 0.051 --0.01 0.081 0.014 0.006 0.394 0.394 0.031 0.520 0.520 0.031 0.063 --0.02 0.087 0.018 0.010 0.398 0.398 0.036 0.530 0.530 0.037 0.075 0.003 0 7
Min. Nom.
--0.05 1.90 0.25 0.101 9.9 9.9 0.635 12.95 12.95 0.65 1.295 --0.25 2.05 0.35 0.152 10.00 10.00 0.80 13.2 13.2 0.8 1.6
Max.
--0.5 2.20 0.45 0.254 10.1 10.1 0.952 13.45 13.45 0.95 1.905 0.08
1
33
E HE
11
12
e
b
22
A A1 A2 b c D E e HD HE L L1 y
Notes:
c
0
7
A2 A A1 y L L1 Detail F
Seating Plane
See Detail F
1. Dimension D & E do not include interlead flash. 2. Dimension b does not include dambar protrusion/intrusion. 3. Controlling dimension: Millimeter 4. General appearance spec. should be based on final visual inspection spec.
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W78E858
11. VERSION HISTORY
VERSION A B C D DATE Oct. 2001 Jul. 2002 Nov. 2002 May. 2004 PAGE 15 5 6 6 Initial Issued Modify timer 2 interrupt vector address EEPROM address of command code Remove erase acquisition flow Add a demo code DESCRIPTION
Headquarters
No. 4, Creation Rd. III, Science-Based Industrial Park, Hsinchu, Taiwan TEL: 886-3-5770066 FAX: 886-3-5665577 http://www.winbond.com.tw/
Winbond Electronics Corporation America
2727 North First Street, San Jose, CA 95134, U.S.A. TEL: 1-408-9436666 FAX: 1-408-5441798
Winbond Electronics (Shanghai) Ltd.
27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998
Taipei Office
9F, No.480, Rueiguang Rd., Neihu District, Taipei, 114, Taiwan, R.O.C. TEL: 886-2-8177-7168 FAX: 886-2-8751-3579
Winbond Electronics Corporation Japan
7F Daini-ueno BLDG, 3-7-18 Shinyokohama Kohoku-ku, Yokohama, 222-0033 TEL: 81-45-4781881 FAX: 81-45-4781800
Winbond Electronics (H.K.) Ltd.
Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064
Please note that all data and specifications are subject to change without notice. All the trade marks of products and companies mentioned in this data sheet belong to their respective owners.
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Publication Release Date: May 5, 2004 Revision A4

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